Field of the Invention
The present invention relates to a signal processing device that performs signal processing with an accuracy within one clock pulse, a signal processing method, and an image forming apparatus for performing signal processing and image formation with an accuracy within one clock pulse, using a group of delayed signals generated by a delay element group delaying a clock.
Description of the Related Art
A known image forming apparatus forms an image equivalent to one line or a few lines in the main scanning direction in accordance with image data, and also forms an image equivalent to one page by repeating, in the sub scanning direction, image formation of each line in the main scanning direction.
In the image formation in the main scanning direction in accordance with image data, positioning is performed based on a clock that serves as the reference clock for the pixels to be formed, or a clock called “pixel clock” or “dot clock”.
For example, an electrophotographic image forming apparatus scans with a laser beam modulated in accordance with image data in the main scanning direction, and at the same time, forms an image with the laser beam on an image bearing member rotating in the sub scanning direction. In this case, the laser beam is modulated with the image data in synchronization with the above described clock.
There is a technique for performing signal processing such as a PWM process with an accuracy within one clock pulse by generating a group of delayed signals with a delay element group delaying the clock in a number of stages, and selecting a delayed signal pulse of a desired time from the group of delayed signals.
FIG. 6 shows a specific example where a signal processing circuit 1 that performs a PWM process with an accuracy within one clock pulse is used in an image forming apparatus.
The flowchart in FIG. 7 shows operation of the signal processing circuit 1. FIG. 8 is a timing chart showing states of various kinds of signals to be processed by the signal processing circuit 1.
A clock generating unit 5 generates the reference clock (reference CLK) at a frequency suitable for forming an image of an originally intended size (step S11 in FIG. 7). Specifically, an image of an originally intended size can be formed by arranging a predetermined number of dots with PWM signals generated with the reference clock (reference CLK) used as the pixel clock.
Here, the clock frequency needs to be adjusted by several percent through adjustment of the size of the images to be formed on the front and back of a paper sheet or partial magnification of images for various kinds of distortion correction or the like. So as to adjust the position of an image on a paper sheet, the clock phase needs to be adjusted in some cases.
A frequency modulating unit 10 generates a modulation clock by minutely adjusting (changing) the frequency of the reference clock. In this case, a delay element group 12 generates a group of delayed signals by minutely delaying the phase of the reference clock (step S14 in FIG. 7). For example, the delay element group 12 delays the pulse of one cycle of the divided reference clock by approximately 1/100 stage, to generate the group of delayed signals. A selecting unit 16 selects a suitable delayed signal from the group of delayed signals, so that the modulation clock having the frequency of the reference clock changed by ±1% can be generated.
A delay amount measuring unit 13 can measure the delay time in one stage of the group of delayed signals based on how many stages of the delayed signals are equivalent to one cycle of the reference clock (step S15 in FIG. 7). In this case, the reference clock is as accurate as crystal oscillation. Accordingly, even if the delay time of the group of delayed signals changes due to temperature or time, it is possible to recognize the delay time.
Frequency modulation coefficient data indicating to what extent the reference clock is to be changed is supplied from outside (step S12 in FIG. 7), and a timing calculating unit 14 refers to the delay time measured by the delay amount measuring unit 13 with respect to one stage of the group of delayed signals, and calculates the necessary number of stages of delayed signals for changing the reference clock to a desired frequency (step S16 in FIG. 7). The selecting unit 16 selects an optimum delayed signal pulse from the group of delayed signals, and outputs the selected pulse as the modulation clock (step S17 in FIG. 7).
For example, an instruction to increase the frequency of a 50 MHz reference clock by 4% is given as the frequency modulation coefficient data. In this case, the number of stages of delayed signals to be selected from the group of delayed signals is gradually changed, so that a modulation clock of 52 MHz, which is 4% higher than 50 MHz as desired, is generated.
Here, “modulation” is not the same as modulation in communications (multiplication of carrier waves by information), but means a change in the frequency of a clock. As suitable delayed signals are selected from the group of delayed signals in generating the modulation clock, it is difficult to accurately obtain a 52 MHz modulation clock. The frequency fluctuates up and down, and a mean frequency of 52 MHz is eventually obtained.
The modulation clock is then input to a synchronizing unit 20 in the next stage. This synchronizing unit 20 has the same circuit configuration as that of the above described frequency modulating unit 10. In this synchronizing unit 20, the phase and the position of the pulse with respect to the modulation clock are changed in accordance with data supplied from outside, and a synchronization clock is generated.
In this case, a delay element group 22 generates a group of delayed signals by minutely delaying the phase of the modulation clock (step S18 in FIG. 7). For example, the delay element group 22 delays the pulse of one cycle of the reference clock by approximately 1/100 stage, to generate the group of delayed signals. A selecting unit 26 selects a suitable delayed signal from the group of delayed signals, so that the phase of the modulation clock can be changed by ±1%, and a synchronization clock synchronized with a predetermined phase can be generated. Here, the synchronization clock is generated so as to be synchronized with sensor data and phase data that are input from outside.
In this synchronizing unit 20 operating in the same manner as the frequency modulating unit 10 described above, sensor data and phase data that indicate with which phase the reference clock is to be synchronized are supplied from outside (step S12 in FIG. 7), and a timing calculating unit 24 refers to the delay time measured (step S19 in FIG. 7) by a delay amount measuring unit 23 with respect to one stage of the group of delayed signals, and calculates the necessary number of stages of delayed signals for synchronizing the modulation clock with a desired phase (step S20 in FIG. 7). The selecting unit 26 selects an optimum delayed signal pulse from the group of delayed signals, and outputs the selected pulse as the synchronization clock (step S21 in FIG. 7).
The synchronization clock is then input to a PWM processing unit 30 in the next stage. This PWM processing unit 30 has almost the same circuit configuration as those of the frequency modulating unit 10 and the synchronizing unit 20 described above. Here, a PWM signal having a pulse width in accordance with the value of image data is generated from the synchronization clock.
In this case, a delay element group 32 generates a group of delayed signals by minutely delaying the phase of the synchronization clock (step S22 in FIG. 7). For example, the delay element group 32 delays the pulse of one cycle of the reference clock by approximately 1/100 stage, to generate the group of delayed signals. A selecting unit 36 selects a suitable delayed signal from the group of delayed signals, so that a PWM signal having a leading edge and a trailing edge selected by ±1% can be generated. Here, a PWM signal is generated so as to have the pulse width corresponding to the value of image data that is input (step S13 in FIG. 7) from outside.
In the PWM processing unit 30 operating in the same manner as the frequency modulating unit 10 and the synchronizing unit 20 described above, a timing calculating unit 34 refers to the delay time measured (step S23 in FIG. 7) by a delay amount measuring unit 33 with respect to one stage of the group of delayed signals and the value of image data, and calculates the number of stages of delayed signals having the necessary edges (leading and trailing edges) for generating a PWM signal of a desired pulse width (step S24 in FIG. 7). A pulse generating unit 36 then selects an optimum delayed signal pulse from the group of delayed signals based on a result of the calculation, and generates the PWM signal (step S25 in FIG. 7).
In accordance with the pulse width of the PWM signal to be generated by the pulse generating unit 36, a dividing unit 31 is provided on the input side of the delay element group 32, and divides the synchronization clock. So as to adjust the timing of the image data to the synchronization clock at the time of the calculation by the timing calculating unit 34, a synchronizing unit 35 synchronizes the image data with the synchronization clock.
In FIG. 8, a group of delayed signals (a1) is generated from the reference clock (a0), desired delayed signals are selected, and the modulation clock (a2) is generated. Here, the reference clock is equivalent to eight pulses of the delayed signals, and the modulation clock is equivalent to seven pulses of the delayed signals. A group of delayed signals (b1) is also generated from the modulation clock (a2), desired delayed signals are selected, and the synchronization clock (b2) is generated. A group of delayed signals (c1) is further generated from the synchronization clock (b2), desired delayed signals are selected, and the PWM signal (c2) is generated. Here, the PWM signal (c2) is generated in a case where the following situation is repeated three times: pixel value=70%, position=right-adjusted, pixel value=30%, and position=left-adjusted.
Relationships between clock synchronization and image data are disclosed in JP 2001-221965 A and JP 2010-194730 A, for example.
In the example described above with reference to FIGS. 6 to 8, the clock frequency can be adjusted in accordance with adjustment of the size of the images to be formed on the front and back of a paper sheet and partial magnification of an image, and the phase of the clock for adjusting the position of an image on a paper sheet can be adjusted.
However, the timing chart shown in FIG. 8 shows an ideal state, and might differ from a state in reality (as shown in the timing chart in FIG. 9, for example).
In FIG. 9, a group of delayed signals (a1) is generated from the reference clock (a0), desired delayed signals are selected, and the modulation clock (a2) is generated.
Here, the reference clock is designed to be equivalent to eight pulses of the delayed signals, and the modulation clock is designed to be equivalent to seven pulses of the delayed signals.
However, when the modulation clock is generated through selection of desired delayed signals from the group of delayed signals, the leading edge or the trailing edge of the modulation clock can be changed only once in one pulse of the reference clock. Therefore, in the example shown in FIG. 9, the number of selected pulses vary from eight pulses to seven pulses to six pulses, for example, with the average being seven pulses.
A group of delayed signals (b1) is also generated from the modulation clock (a2), desired delayed signals are selected, and the synchronization clock (b2) is generated. A group of delayed signals (c1) is further generated from the synchronization clock (b2), desired delayed signals are selected, and the PWM signal (c2) is generated.
In FIG. 9, the group of delayed signals (a1), the group of delayed signals (b1), and the group of delayed signals (c1) are delayed signal groups that are generated independently of one another. Therefore, the pulses appear to be the same in the schematic diagram in FIG. 9, but in practice, each pulse contains an error component.
Here, the PWM signal (c2) is generated in a case where the following situation is repeated three times: pixel value=70%, position=right-adjusted, pixel value=30%, and position=left-adjusted.
At a portion d11 of the PWM signal, there is a blank portion at the portion that is right-aligned and is 70% in pixel value. This is because, where the pixel value is 70%, one clock is assumed to be seven pulses, and the start is moved to the right by two pulses. In practice, however, one clock is eight pulses, and a blank portion equivalent to one pulse is formed at the right end portion.
At a portion d12 of the PWM signal, the portion that is right-aligned and is 70% in pixel value is smaller than the originally intended size. This is because, where the pixel value is 70%, one clock is assumed to be seven pulses, and the start is moved to the right by two pulses. In practice, however, one clock is six pulses, and therefore, the one pulse at the right end portion is left out. Having been subjected to the frequency modulation, the synchronizing process, and the PWM process as described above, the PWM signals based on the same image data do not have the same pulse widths as one another. This leads to image quality deterioration.
As is apparent from FIGS. 6 and 7, in the entire apparatus, the three delay element groups positioned in series generate the respective groups of delayed signals. As a result, delay variations that occur in the respective delay element groups accumulate.
If delay variations are completely random and do not have correlation with one another, the delay variations are not multiplied (three times) by the three stages in some cases. However, the same delay element groups are used in the same environments in this case. Therefore, delay variations in the same direction accumulate, and are predicted to actually lead to a large delay variation.
Since different frequencies and different phases are used in generating the modulation clock from the reference clock, generating the synchronization clock from the modulation clock, and generating the PWM signal from the synchronization clock, the respective delay element groups need to be provided independently of one another, and cannot be integrated into one delay element group.
Specifically, in a case where a group of delayed signals generated by a delay element group delaying the clock, and signal processing is performed with an accuracy within one clock pulse in the respective stages of the clock frequency modulation, the clock synchronization, and the PWM process, delay variations of the delay elements accumulate, leading to a large error. Due to the delay variations, the pulse widths of PWM signals (or densities in an image forming apparatus) vary, and image quality deterioration is caused.
Since a delay element group is required for each function, the circuit size becomes large. In a case where minute delay times are set so as to cope with high resolution, the circuit size of each delay element group becomes large, and therefore, the problem of circuit size becomes a very serious issue.
Although image densities in an image forming apparatus have been described as a specific example, the image densities can be regarded as signal values in a signal processing device.
Any of the above mentioned patent literatures cannot solve the above problem, and do not consider the above problem as a serious issue.